Sudeb Dasgupta & Brajesh Kumar Kaushik 
Spacer Engineered FinFET Architectures 
High-Performance Digital Circuit Applications

This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the Fin FET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.