Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware.
In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems.
This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.
สารบัญ
- Preface to the Second Edition
- Preface to the First Edition
- Introduction to Consistency and Coherence
- Coherence Basics
- Memory Consistency Motivation and Sequential Consistency
- Total Store Order and the x86 Memory Model
- Relaxed Memory Consistency
- Coherence Protocols
- Snooping Coherence Protocols
- Directory Coherence Protocols
- Advanced Topics in Coherence
- Consistency and Coherence for Heterogeneous Systems
- Specifying and Validating Memory Consistency Models and Cache Coherence
- Authors’ Biographies
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